Project Description

The goal of this project is the exploration and analysis of physical attacks on a RISC-V processor. RISC-V is an open source architecture for designing processors that has gained high adoption in the industry. We will be implementing a five stage single-issue in-order pipelined RISC-V CPU based on the 32-bit RISC-V integer (rv32i) instruction set. A reference implementation is the DINO CPU [paper, code] which is written in Chisel. However, for this project, our implementation will be based on ArchLab’s PyRTL [paper, code]. We will be analyzing the vulnerabilities of this core based on side-channel attacks and fault-injection attacks. In particular, we will be looking at how symmetric block ciphers like AES is vulnerable to these attacks. Based on this analysis, we will be suggesting architectural countermeasures and evaluating the overhead of these countermeasures in terms of performance and resources. 

Knowledge that must be acquired:

  • Fundamentals of hardware and architecture design (books and resources are available to do this specifically focusing on RISC-V, e.g., Computer Organization and Design RISC-V Edition: The Hardware Software Interface by Patterson and Hennesey)
  • Hardware Design Language: PyRTL (Python)/Verilog and familiarity with Chisel (based on Scala)
  • Basic hardware/processor security and cryptography concepts

Notes:

Aside from the main project, we will be writing a survey paper (or SoK) on physical attacks on RISC-V processors which we will target as a conference/journal [TBD] submission

Team Members

  • Tyler Ekairab
  • Bethany Long
  • Vincent Benenati
  • Ethan Scott

Professor and Mentors

  • Professor Timothy Sherwood
  • Alvin Glova
  • Aarti Jivrajani

Meeting Time

  • Group Meeting: Thursday, 3:30-4:30 PM

Links to Proposals and Presentations

Individual Logs

Peer Review

Project Documentation